Shakti is processor developed by India. The Indian Institute of Technology in Madras has has released the software development kit (SDK) for its open-source Shakti processor. Shakti is based on the open-source RISC-V instruction set architecture and was funded by the Indian Ministry of Electronics and Information Technology. The institute promised that a development board will also be released soon. With the release of the Shakti SDK, developers can begin to develop applications for the Shakti processors, even before they’re commercialized.
Shakti processor has divided in 3 categories.
This is a 32-bit 5 stage in-order microcontroller-class of processors supporting 0.2-1 GHz clock speeds. It’s aimed at mid-range application workloads and has a very low power profile, plus support for optional memory protection.
The E class is a 3-stage in-order processor targeted at embedded devices such as Internet of Things (IoT) devices, robotic platforms, motor controls, etc.
The I class 64-bit out-of-order processors support 1.5-2.5 GHz clock speeds and support for multi-threading. It targets mobile, storage and networking applications.
These are processors for the high-performance computing and analytics workloads. Their primary features include a high single-thread performance, optional L4 cache, as well as support for Gen-Z fabric and storage-class memory.
The M stands for multi-core here, as the M class processors support up to eight CPU cores, which can also be I and C class cores.
The S class of Shakti processors is aimed at workstation and server-type workloads. It’s an enhanced version of the I class processor that features multi-threading support.
This category of cores are experimental in nature and will include variants of the base-class processors modified to meet specific criteria.
T class, which should support object-level security and coarse grain tags for micro-VM-like functionality to mitigate software attacks like buffer-overflow.
F class, which can be thought of as an upgrade over the T class with additional support for redundant compute blocks and bus fabrics, ECC memory and functionality to detect permanent faults.